The present invention relates to a solid-state imaging device constructed in accordance with a TSL (Transversal Signal Line) system capable of producing an image free from smearing by reading pixel signals through signal read lines interconnected in a horizontal scanning direction.
MOS-type solid-state imaging devices having a construction as shown in FIG. 5 have been widely used.
This type of solid-state imaging device, which is formed using semiconductor fabrication techniques, includes a light-receiving region 1 for receiving an optical image, a vertical scanning circuit 2, and a horizontal scanning circuit 3 for reading pixel signals.
The light-receiving region 1 has a plurality of photodiodes P.sub.11 to P.sub.nm (where n designates a row position and m, a column position) arrayed in matrix form. Between the photodiodes P.sub.11 to P.sub.nm are vertical selection gate lines L.sub.1 to L.sub.n, each extending from a respective bit output b.sub.1 to b.sub.n of the vertical scanning circuit 2, which is implemented with shift registers, and signal read lines l.sub.1 to l.sub.m.
Further, as shown in the figure, between the photodiodes P.sub.11 to P.sub.nm and the signal read lines l.sub.1 to L.sub.m are connected switching transistors M.sub.11 to M.sub.nm formed of MOS-type field effect transistors (FETs). Each of the switching transistors M.sub.11 to M.sub.nm is turned on and off in accordance with a vertical scanning signal applied from the vertical scanning circuit 2 through respective ones of the vertical selection gate lines L.sub.1 to L.sub.n, thereby to sequentially transmit the pixel signals of the photodiodes P.sub.11 to P.sub.nm to the signal read lines l.sub.1 to L.sub.n every row.
Further, the terminal of each of the signal read lines l.sub.1 to l.sub.n is connected to an output line 4 through switching transistors N.sub.1 to N.sub.m, each composed of a MOS-type FET, for horizontal scanning. Horizontal selection gate lines a.sub.1 to a.sub.m extending from bit output contacts h.sub.1 to h.sub.m of the horizontal scanning circuit 3 are connected to the gate contacts of switching transistors N.sub.1 to N.sub.m, respectively. Each of the switching transistors N.sub.1 to N.sub.m is turned on and off in accordance with a horizontal scanning signal applied from the horizontal scanning circuit 3 through respective ones of the horizontal selection gate lines a.sub.1 to a.sub.m, thereby to sequentially transmit pixel signals present on the signal read lines L.sub.1 to l.sub.m to the output line 4 and output pixel signals S (n,m) from an output terminal 5 in time sequence.
In this way, the pixel signals generated by the photodiodes P.sub.11 to P.sub.nm are read at a timing specified by the vertical scanning circuit 2 and the horizontal scanning circuit 3, thereby allowing all the pixel signals to be read.
However, the MOS-type solid-state imaging device thus constructed vertically scans an image every predetermined horizontal scanning period using the vertical scanning circuit 2, and horizontally scans the image within each horizontal scanning period using the horizontal scanning circuit 3 in a point-sequential manner. Thus, each of the signal output lines l.sub.1 to l.sub.m is scanned once every horizontal scanning period, and as a result, a noise component is superimposed on each of the signal read lines l.sub.1 to l.sub.m while waiting for a next scanning operation, thereby causing smearing.
In order to prevent smearing, a MOS-type solid-state imaging device having such a construction as shown in FIG. 6 has been developed. This device is a MOS-type solid-state imaging device of a TSL system, and is distinguished from the solid-state imaging device shown in FIG. 5 in the following points.
Two series-connected switching transistors are connected to each of the photodiodes P.sub.11 to P.sub.nm, and one of the switching transistors which is adjacent to the photodiode is vertically scanned by the vertical scanning circuit 2, while the other switching transistor is horizontally scanned by the horizontal scanning circuit 3. When both switching transistors are turned on, a pixel signal from the photodiode corresponding to these switching transistors is read through the horizontally extending signal read line.
Referring to FIG. 6, reference characters L.sub.1 to L.sub.n designate vertical selection gate lines; l.sub.1 to l.sub.n, signal read lines; a.sub.1 to a.sub.m, horizontal selection gate lines; Q.sub.1 to Q.sub.n, switching transistors interposed between the signal read lines l.sub.1 to l.sub.n and the output line 4, and which are sequentially turned on in synchronism with a vertical scanning signal transmitted from the vertical scanning circuit 2 through the vertical selection gate lines L.sub.1 to L.sub.n.
The construction of an element E will be more specifically described as a representative example. The two switching transistors f and g are connected in series between the photodiode M.sub.11 and the signal read line l.sub.1. The vertical selection gate line L.sub.1 is connected to the gate contact of the switching transistor f, while the horizontal selection gate line a.sub.1 is connected to the gate contact of the other switching transistor g. The pixel signal of the photodiode M.sub.11 is read to the output terminal 5 through the signal read line l.sub.1 and the output line 4 while turning the switching transistor g on with the switching transistors f and Q.sub.1 turned on by applying a vertical scanning signal from the vertical scanning circuit 2.
The vertical scanning signal is sequentially transmitted from the bit outputs b.sub.1 to b.sub.n to the vertical selection gate lines L.sub.1 to L.sub.n of the vertical scanning circuit 2 every predetermined horizontal scanning period, and then horizontal scanning signals are sequentially transmitted within the respective cycles from the bit outputs h.sub.1 to h.sub.m to the horizontal selection gate lines a.sub.1 to a.sub.m of the horizontal scanning circuit 3, thereby allowing all the pixel signals to be read in sequence.
In the solid-state imaging device of such a TSL system, each pixel signal is applied through its signal read line in synchronism with the horizontal scanning-based point sequential scanning cycle. Therefore, the period in which a noise component can be mixed in the signal read line is shorter than o that in the case of the solid-state imaging device shown in FIG. 5, thereby causing smearing to be remarkably reduced.
FIG. 7 shows the construction of a portion of the light-receiving region of the solid-state imaging device of the TSL system shown in FIG. 6. The plan structure of nine pixels is shown as an example.
In the figure, reference character M designates an n.sup.+ impurity region embedded in the surface region of a P-well layer formed in a semiconductor substrate, each region M forming a photodiode corresponding to a pixel.
Further, a terminal portion of each n.sup.+ impurity region extends in L form, and the L-formed terminal portions are connected to the signal read lines l.sub.i, l.sub.i+1, l.sub.i+2 (indicated by a one-dot chain line) made of a first aluminum layer through a contact (designated by ). Each of the signal read lines l.sub.i, l.sub.i+1, l.sub.i+2 is formed so as to run transversely between the n.sup.+ impurity regions constituting the pixels, and is connected to the output line 4 through a predetermined switching transistor among the switching transistors Q.sub.1 to Q.sub.n shown in FIG. 6.
Each of vertical gate lines L.sub.i, L.sub.i+1, L.sub.i+2, which formed of a polysilicon layer (shown by a solid line), is laminated so as to be adjoining to each of the signal read lines l.sub.i, l.sub.i+1, l.sub.i+2. The polysilicon layer extending from the side of each of the vertical selection gate lines L.sub.i, L.sub.i+1, L.sub.i+2 covers the upper surface of the L-formed portion in each n.sup.+ impurity region. The MOS-type FET switching transistor for vertical scanning (designated by f) is formed by implanting ions in the n.sup.+ impurity region close to the covered portion. Each of the vertical selection gate lines L.sub.i, L.sub.i+1, L.sub.i+2 is connected to a predetermined bit output contact of the vertical scanning circuit 2 shown in FIG. 6.
Further, the horizontal selection gate lines a.sub.j, a.sub.j+1, a.sub.j+2 are formed of a second aluminum layer (shown by the dotted line) extending vertically between the n.sup.+ impurity regions constituting the respective pixels. A gate portion (designated by F) made of a polysilicon layer that covers the other upper surface of the L-formed portion of the n.sup.+ impurity region is connected to the side end of each of the horizontal selection gate lines a.sub.j, a.sub.j+1, a.sub.j+2 through a contact (designated by ). The MOS-type FET (designated by g) for horizontal scanning is formed by implanting ions in the n.sup.+ impurity region adjacent to the portion covered by the gate contact. Here, each of the horizontal selection gate lines a.sub.j, a.sub.j+1, a.sub.j+2 is connected to a predetermined bit output of the horizontal scanning circuit 3 shown in FIG. 6.
The first and second aluminum layers and the polysilicon layer are formed by respective masking processes, and laminated one upon the other through a silicon oxide film layer so as to be insulated from each other.
In the above construction, the vertical scanning circuit 2 and the horizontal scanning circuit 3 perform vertical scanning and horizontal scanning to turn on the switching transistors f and g sequentially at a predetermined timing. As a result, each pixel signal produced at each photodiode can be read in sequence.
However, in such a conventional solid-state imaging device arranged in accordance with the TSL system, as shown in FIG. 7, the drain portions of each pair of switching transistors interposed between each photodiode and each signal read line are not only formed integrally of the same impurity layer as that of the photodiode, but also are of such construction that they are not entirely shielded. Therefore, stray charges induced due to externally incident light are mixed in the pixel signals as a noise.
In addition, to form the vertical and horizontal selection gate lines and the signal read lines, it is necessary to have a total of three layers, i.e., two aluminum layers and one polysilicon layer, thus requiring increased process steps, impairing the yield, and increasing the manufacturing cost.
Moreover, such a conventional solid-state imaging device of the TSL system cannot provide a sufficient dynamic range to prevent saturated exposure. That is, in this solid-state imaging device in which the pixel signal (charges) stored in the photodiode is read through the signal read line, insufficient capacitance of the signal read line may leave some pixel signals unread. Therefore, it is the capacitance of the signal read line that determines the dynamic range of the device. However, the capacitance of the conventional signal read lines (l.sub.i, l.sub.i+1, l.sub.i+2 in FIG. 7) is determined by a parasitic capacitance present between the aluminum layer and the semiconductor substrate. In such a construction, a silicon oxide film layer is employed as a dielectric. This silicon oxide film layer serves to insulate the aluminum layer from the semiconductor substrate. Since this silicon oxide film layer is thick, its capacitance is small, thereby preventing the dynamic range from being increased. In particular, as the number of switching transistors formed between the pixel constituting photodiode and the signal read line is increased, i.e., as the number of pixels is increased, it is necessary to increase the capacitance of each signal read line. However, the higher degree of integration due to increased number of pixels makes it difficult to take measures such as increasing the width of the signal read line, thereby preventing the dynamic range from being increased. On the other hand, if the width of the signal read line is increased to increase the dynamic range, the numerical aperture is decreased, thereby reducing the sensitivity and the like of the device.
In addition, the device is of such a structure as to require that a total of three layers, two aluminum layers and one polysilicon layer, be arranged to form the vertical and horizontal selection gate lines and the signal read lines. This increases the number of steps of the manufacturing process, thereby impairing the yield and increasing the manufacturing cost.